Quantum and reversible logic circuits have more advantages than the common circuits, like low power consumption. These circuits are good choice to design future computers. One of the important issues in reversible logic is parity preservation. If parity of inputs and outputs are equal in reversible gate, this gate will be parity preserve. Reversible circuits made by these gates are parity preserve. In this paper we propose a new fault tolerant reversible divider. The proposed fault tolerant reversible divider is the first effort to design fault tolerant reversible division circuit. In this circuit, we use some fault tolerant reversible components like fault tolerant reversible parallel adder, fault tolerant reversible shift register and fault tolerant reversible n-bit register. Hence, we also propose a new fault tolerant reversible full adder, a new fault tolerant reversible n+1-bit parallel adder and a new basic cell for PIPO fault tolerant reversible left-shift register. These parity preserving reversible components are also proposed for the first time in the literature. All the scales are in the nanometric area.
Key words: Reversible logic, parity preservation, fault tolerant, nanometric circuits, reversible divider.
Copyright © 2023 Author(s) retain the copyright of this article.
This article is published under the terms of the Creative Commons Attribution License 4.0