Journal of
Engineering and Technology Research

  • Abbreviation: J. Eng. Technol. Res.
  • Language: English
  • ISSN: 2006-9790
  • DOI: 10.5897/JETR
  • Start Year: 2009
  • Published Articles: 190

Article in Press

Fault tolerance in reversible logic circuits and quantum cost optimization

A. Kamaraj and P. Marichamy

  •  Received: 28 March 2020
  •  Accepted: 03 July 2020
Energy dissipation has a prominent factor for the very large scale integrated circuit (VLSI). The reversible logic-based circuit was capable to compute the logic without energy dissipation. Accordingly, reversible circuits are an emerging domain of research based on the low value of energy dissipation. At nano-level design, the critical factor in the logic computing paradigm is the fault. The proposed methodology of fault coverage has powerful for testability. In this article, we target three factors such as fault tolerance, fault coverage and fault detection in the reversible KMD Gates. Our analysis provides good evidence that minimum test vector covers the 100% fault coverage and 50% fault tolerance in KMD Gate. Further, we show a comparison between the quantum equivalent and controlled V and V+ gate in all the types of KMD Gates. The proposed methodology mentions that after controlled V and V+ gate based ALU, divider and Vedic multiplier have a significant reduction in quantum cost. The comparative results of designs such as Vedic multiplier, division unit and ALU are obtained and it is analyzed and its significant improvement in quantum cost.

Keywords: KMD Gate, Controlled V and V+ gate, ALU, Divider and Vedic multiplier