Instability of SRAM memory cells derived from aggressive technology scaling has recently been one of the most significant issues. Although a 7T–SRAM cell with an area tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. A new memory cell adopting a look ahead body-bias which dynamically controls the threshold voltage was proposed in order to assist the write operation. Simulation results have shown improvement in both the write margins and access time.
Key words: Body-bias, SRAM, low power design.
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