Abstract

This paper describes the field programmable gate array (FPGA) implementation of a fast 2-D discrete cosine transform (DCT) chip for higher image compression ratio. The development of encoding and decoding parts of 2-D DCT algorithm is carried out by using Matlab simulation tools and VHSIC hardware descriptive language (VHDL). Comparisons of results for higher image compression ratio as obtained by using Matlab are presented. To improve a fast processor, we have also enhanced the functionality of the arithmetic logic unit (ALU) block in the DCT chip in order to design a fast 2-D DCT chip. The developed VHDL code of the 2-D DCT algorithm is incorporated with the VHDL codes of the enhanced ALU block. The synthesis software, Quartus-II integrated synthesis (QIS) from Altera has been used to obtain hardware blocks for the fast 2-D DCT processor. Performance evaluation of the 2-D DCT processor was achieved using Altera digital library from FPGA technology (TSMC 90 nm). The evaluated parameters are given such as maximum clock frequency of 140 MHz, total power dissipation of 638.84 mW and number of adaptive logic modules (ALMs) as 128. The enhanced 2-D DCT chip is intended for wireless image communication applications.

Key words: 2-D discrete cosines transform (DCT), image transforms, VHSIC hardware descriptive language (VHDL), synthesis, field programmable gate array (FPGA).