International Journal of
Physical Sciences

  • Abbreviation: Int. J. Phys. Sci.
  • Language: English
  • ISSN: 1992-1950
  • DOI: 10.5897/IJPS
  • Start Year: 2006
  • Published Articles: 2569


Design of fast fault tolerant reversible signed multiplier

Xuemei Qi1,2,3*, Fulong Chen1,2, Kaizhong Zuo1,2, Liangmin Guo1,2, Yonglong Luo1,2and Min Hu3
  1School of Mathematics and Computer Science, Anhui Normal University, Wuhu 241003, P.R. China.     2Network and Information Security Engineering Research Center, Anhui Normal University, Wuhu 241003, P.R. China.   3School of Computer and Information, Hefei University of Technology, Hefei 230009, P.R. China.
Email: [email protected]

  •  Accepted: 10 April 2012
  •  Published: 30 April 2012



Reversible logic circuits are emerging as a promising technology for power minimization. Parity preserving reversible circuits design will be very important for development of fault tolerant reversible systems in nanotechnology. In this paper, a fast fault tolerant reversible signed multiplier is proposed. In order to construct the multiplier, five variables parity preserving gate (F2PG) and modified new fault tolerant (MNFT) are designed, which are parity preserving reversible gates. The most significant aspect of F2PG is that it can work independently as a reversible fault tolerant full adder. Meanwhile, it can implement all Boolean functions. MNFT can reduce cross redundancy. The quantum implementations of F2PG and MNFT are also given. Otherwise, a new quantum implementation of the modified Islam gate (MIG) is presented. The Wallace tree is applied to improve the operating speed of the multiplier, which can implement the multiplication of two 5-bit binary signed numbers. Simulation and evaluation results indicate that the multiplier logic structure is correct with excellent performance.


Key words: Parity preserving reversible gate, fault tolerant, five variables parity preserving gate (F2PG), modified new fault tolerant (MNFT), reversible signed multiplier.