Abstract

This paper investigates the effect of gate electrode work function in 30 nm gate length conventional and junctionless FinFETs using technology computer-aided design (TCAD)simulations. DC parameters, threshold voltage (v_t), drive current (I_on) and output resistance (R_o), and RF parameters, unity gain cut-off frequency (f_t), non-quasi static (NQS) delay and input impedance (Z₁₁) are investigated. Junctionless devices being bulk conductive behaves differently with respect to work function variation compared to surface conducting conventional devices. The rate of change in V_t and I_on with respect to work function, in junctionless devices, is slower compared to conventional devices. Owing to better drain induced barrier lowering (DIBL) performance, junctionless devices have higher output resistance. In conventional devices, f_t is not sensitive for most of the work function range due to the screening effect of the inversion layer whereas junctionless device shows strong dependency on the work function.

Key words: FinFET, Junctionless transistor, work function, drain induced barrier lowering (DIBL), technology computer-aided design (TCAD).