Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

H. A. Elgomati; B. Y. Majlis; I. Ahmad; F. Salehuddin; F. A. Hamid; A. Zaharim; T. Z. Mohamad; P. R. Apte

doi:10.5897/IJPS11.151

International Journal of
Physical Sciences

Abbreviation: Int. J. Phys. Sci.
Language: English
ISSN: 1992-1950
DOI: 10.5897/IJPS
Start Year: 2006
Published Articles: 2572

Full Length Research Paper

Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

H. A. Elgomati1*, B. Y. Majlis1, I. Ahmad2, F. Salehuddin2, F. A. Hamid2, A. Zaharim3, T. Z. Mohamad4 and P. R. Apte5

1Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia (UKM) 43600 Bangi, Selangor, Malaysia. 2College of Engineering, Universiti Tenaga Nasional (UNITEN) 43009 Kajang, Selangor, Malaysia. 3Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia (UKM)343600 Bangi, Selangor, Malaysia. 4Test 2 Operation, Freescale (M) Sdn. Bhd. P. O. Box 1001, Jln Semangat 47300 Petaling Jaya, Selangor D.E., Malaysia. 5Indian Institute of Technology (IIT) Bombay, Powai, Mumbai-400076, India.
Email: [email protected]

Article Number - C86473923773
Vol.6(10), pp. 2372-2379 , May 2011
https://doi.org/10.5897/IJPS11.151

Accepted: 01 April 2011
Published: 18 May 2011

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