International Journal of
Physical Sciences

  • Abbreviation: Int. J. Phys. Sci.
  • Language: English
  • ISSN: 1992-1950
  • DOI: 10.5897/IJPS
  • Start Year: 2006
  • Published Articles: 2557

Full Length Research Paper

Frequency synthesis techniques for high speed communication system

Govind Singh Patel1* and Sanjay Sharma2
1Department of Electronics and Communication Engineering, Lingayas University, Haryana, India. 2Department of Electronics and Communication Engineering, Thapar University, Punjab, India.
Email: [email protected]

  •  Accepted: 28 March 2011
  •  Published: 04 June 2011


The phase locked loop (PLL) has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. We used DDS and two types of PLLs analog as well as digital in our work. Though we gave a comparative results of PLLs used in our simulation based on their settling time. Second frequency technique, the Direct Digital Frequency Synthesis (DDFS) is a kind of frequency synthesizer that uses electronic methods for digitally creating arbitrary waveforms and frequencies from a single, fixed source frequency. DDFS is a mixed signal part. DDFS’s digital part is also known as Numerically Controlled Oscillator, which consists of a Phase Register, a Phase Accumulator and a ROM. The analog part has Digital-to-Analog Converter and a filter. NCO is a digital computing block which renders digital word sequences in time at a given reference clock frequency fclk, which thereafter are converted into analog signals to serve as a synthesizer. In this work we analyzed the simulated results of DDS and the different PLLs used for frequency synthesis using tools Xilinx and Matlab.


Key words: Phase locked loop (PLL), Direct Digital Synthesis (DDS), communication system, frequency synthesis.