An FPGA realization of simplified turbo decoder architecture

Shivani Verma; Kumar S.

doi:10.5897/IJPS11.424

International Journal of
Physical Sciences

Abbreviation: Int. J. Phys. Sci.
Language: English
ISSN: 1992-1950
DOI: 10.5897/IJPS
Start Year: 2006
Published Articles: 2572

Full Length Research Paper

An FPGA realization of simplified turbo decoder architecture

Shivani Verma1* and Kumar S.2

1Department of Electronics and Communication Engineering, ASET, Bijwasan, New Delhi, India. 2Department of Electronics and Communication Engineering, Thapar University, Patiala, Punjab, India.
Email: [email protected]

Article Number - D909F5923659
Vol.6(10), pp. 2338-2347 , May 2011
https://doi.org/10.5897/IJPS11.424

Accepted: 07 April 2011
Published: 18 May 2011

Copyright © 2024 Author(s) retain the copyright of this article.
This article is published under the terms of the Creative Commons Attribution License 4.0.

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International Journal of Physical Sciences

An FPGA realization of simplified turbo decoder architecture

Shivani Verma1* and Kumar S.2

International Journal of
Physical Sciences