International Journal of
Science and Technology Education Research

  • Abbreviation: Int. J. Sci. Technol. Educ. Res.
  • Language: English
  • ISSN: 2141-6559
  • DOI: 10.5897/IJSTER
  • Start Year: 2010
  • Published Articles: 71

Full Length Research Paper

Vanishing of clock power consumption by using provisional pulse enhancement scheme

A. Saisudheer
  • A. Saisudheer
  • M. Tech (vlsisd), Tirupathi, India
  • Google Scholar


  •  Received: 15 August 2013
  •  Accepted: 07 July 2014
  •  Published: 29 September 2014

Abstract

In this paper, first a low-power pulse-triggered flip-flop (FF), a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on United Microelectronics Corporation and Complementary metal–oxide–semiconductor (UMC CMOS) 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52.
 
Key words: Flip-flop, low power, pulse-triggered, pulse enhancement.