This paper describes the hardware implementation of Lapped Biorthogonal Transform (LBT) on Field-Programmable Gate Array (FPGA) for JPEG XR Image compression. The implementation is based on dividing image into 128×128 dimension tiles with each tile processed independently. Two main operations that is, overlap pre-filtering and forward core transform are applied on each tile. The proposed design has small memory requirement due to fix 128×128 tile size processing. The hardware design is tested on Xilinx Virtex-II Pro FPGA. The design utilizes 262,144 memory bits, 5824 number of slices and maximum speed is 107.308 MHz.
Key words: Lapped Biorthogonal Transform (LBT), Field-Programmable Gate Array (FPGA), image compression, implementation.
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