Scientific Research and Essays

  • Abbreviation: Sci. Res. Essays
  • Language: English
  • ISSN: 1992-2248
  • DOI: 10.5897/SRE
  • Start Year: 2006
  • Published Articles: 2754

Full Length Research Paper

Synthesis of Chebyshev-I filter using folding and retiming

Nongmaithem Lalleima Chanu
  • Nongmaithem Lalleima Chanu
  • Department of ECE, M-Tech Digital Electronics, DIT Dehradun, India – 248009.
  • Google Scholar
Vimal Kant Pandey
  • Vimal Kant Pandey
  • Department of ECE, M-Tech Digital Electronics, DIT Dehradun, India – 248009.
  • Google Scholar


  •  Received: 25 February 2014
  •  Accepted: 09 April 2014
  •  Published: 30 April 2014

References

Deepa Y, Vijaya K (2012). High Speed Digital Filter using register minimization retiming and Parallel Prefix Adders. IEEE 3rd International Conference on EAIT. pp. 449-453.
 
Edward AL (1991). Consistency in Data Flow Graph. IEEE Trans. Parallel Distrib. Syst. 2:225-235.
 
Jackson LB, Keiser JF, Donald HS (2003). An approach to implementation of Digital Filters. IEEE Trans. Audio Electroacoust. 16(3):413-421.
Crossref
 
John GP Dimitris GM (1996). Digital Signal Processing Principles, Algorithms and Applications. Pearson Education (3rd ed.), Chapters 7 and 8.
 
Keshab KP (2012). VLSI Digital Signal Processing Design and Implementation. In Wiley Student (ed.), Chapters 4 and 5.
 
Keshab PK, Wang CY, Brown AP (1992). Synthesis of Control Circuits in Folded Pipelined Architecture. IEEE J. Solid State Circuit. 27(1):29-43.
Crossref
 
Leiserson C, Rose F, Saxe J (1986). Optimizing Synchronous Circuitry by Retiming. Third Caltech Conf. VLS I:87-116.
 
Monteiro DS, Ghosh A (1993). Retimimg Sequential Circuit for low power. In Proc. IEEE Int. Conf. Comput. Aided Design. pp. 398-402.
 
Parhi KK (1992). Synthesis of DSP data format converted using lifetime analysis and forward-backward register allocation. IEEE Trans. Circuit Systems-II. 39(7):423-440.
Crossref
 
Rajalakshmi K, Arumugam K, Priya MS (2013). Folded Architecture for Digital Gammatone Filter used in Speech Processor of Cochlear Implant. ETRI. J. 35(4).
 
Rajapadhy S, Kiaei S (1991). A folding transformation for VLSI IIR filter array design. Int. Conf. Acoust. Speed Sig. Process. 9:1237-1240.
 
Rakshi S, Premananda BS, Mahir NM (2010). Synthesis of DSP System using Data Flow Graph for silicon area reduction. IJCSIT. 1(5).337-341.
 
Salivahanan S, Vallavaraj A, Gnanapriya C (2010). Digital Signal Processing. (2nd ed.), Tata McGraw Hill.