International Journal of
Physical Sciences

  • Abbreviation: Int. J. Phys. Sci.
  • Language: English
  • ISSN: 1992-1950
  • DOI: 10.5897/IJPS
  • Start Year: 2006
  • Published Articles: 2568

Full Length Research Paper

High voltage buried step-doping p+ layer silicon-on-insulator lateral double diffused mosfet (SOI LDMOSI) with a back-gate

Xiaoming Yang1,2*, Bo Zhang1 and Xiaorong Luo1      
1State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China. 2School of Electrical and Information, Xihua University, Chengdu 610039, China.  
Email: [email protected]

  •  Accepted: 05 July 2011
  •  Published: 02 October 2011

Abstract

A high voltage buried step-doping p+layer (BSP+L) lateral double diffused mosfet (LDMOS) on silicon-on-insulator (SOI) with a back-gate is proposed. The new structure is characterized by a BSP+L on the buried oxide under the source. When a high positive bias is applied to the back-gate in the off-state, the depleted BSP+L greatly enhances the electric field in the buried oxide layer under the source. Compared with conventional SOI LDMOS, much higher vertical breakdown voltage is sustained by the buried oxide layer under the source. Moreover, the reduced surface electric field (RESURF) effect is enhanced by the BSP+L, resulting in improvement of lateral breakdown voltage. Simulation results show that breakdown voltage of the new structure is improved greatly while on-resistance is relatively low.

 

Key words: Silicon-on-insulator, breakdown voltage, back-gate, buried step-doping p+ layer.

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This article is published under the terms of the Creative Commons Attribution License 4.0

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