Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device
F. Salehuddin1,5*, I. Ahmad1, F. A. Hamid1, A. Zaharim2, U. Hashim3 and P. R. Apte4
1College of Engineering, Universiti Tenaga Nasional (UNITEN), Kajang, Selangor, Malaysia.
2Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia.
3School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP), Arau Perlis, Malaysia.
4Indian Institute of Technology (IIT), Bombay, Powai, Mumbai, India.
5Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Durian Tunggal, Melaka, Malaysia.
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